In recent years, a system-on-chip (hereinafter referred to as “SOC”) having a CPU (central processing unit) and a memory mounted on a single semiconductor chip has been developed. This SOC has the advantage that the bus width between the CPU and the memory can be increased, and is incorporated into a system as a constituent element. In this SOC, since the capacity of a mountable memory is limited according to the size of the chip, it is important to efficiently use the mounted memory.
There are various kinds of audio compression methods (Codec), such as MPEG1 Audio and MPEG2 Audio, which are recently used in music distribution and portable audio devices. In these methods, if a system for executing compression and expansion of audio data is constructed of a plurality of CPUs (multiprocessor), the load can be divided and a process which takes time with a single CPU can be processed at high speed. In other words, for example, by allocating a CPU to each codec, it is possible to realize the transcoding operation of decoding data through a first CPU and simultaneously encoding the decoded data through a second CPU, and the operation of performing parallel encoding through different codecs.
FIG. 5 is a block diagram showing the construction of a conventional information processing system. As shown in FIG. 5, the conventional information processing system is equipped with a bus 3 as well as a chip 1, an external memory 110, a host CPU 111 and a server 120, all of which are interconnected by the bus 3. The chip 1 includes an internal memory 101, a DMA (Direct Memory Access) controller 102 which transfers an executable code or data from the external memory 110 directly to the internal memory 101, a first CPU 103, a second CPU 104, and a boot memory 105. The internal memory 101 formed in the chip 1 and the DMA (Direct Memory Access) controller 102, the first CPU 103, the second CPU 104 and the boot memory 105 are interconnected by a bus formed in the chip 1.
The chip 1 having the above-mentioned construction is called a “loosely-coupled multiprocessor” because the chip 1 is equipped with a plurality of CPUs which operate independently of one another and share the internal memory 101.
In the information processing system having the above-mentioned construction, first, bootstraps for the first CPU 103 and the second CPU 104 are stored into the boot memory 105 in accordance with an instruction from the host CPU 111. Then, the first CPU 103 and the second CPU 104 download an executable code from the external memory 110 or the server 120 on a network to the internal memory 101 by using the DMA controller 102 in accordance with the respective bootstraps, and activate the system.
The executable code is generated in the following manner. As shown in FIG. 6, programs created for the respective CPU provided in the chip 1 (a program for the first CPU and a program for the second CPU) and a program to be shared by a plurality of CPUs (a common library program) are compiled to generate object codes corresponding to the respective programs (an object code for a CPU 0, an object code for a CPU 1, and a common library object code).
Then, these object codes are linked to link information 505 containing top addresses for designating locations in the internal memory 101, and an executable code is generated. Accordingly, an executable code 506 thus generated describes instructions and data as well as allocation addresses in the internal memory 101. FIG. 6 shows by way of example the executable code 506 for causing the first CPU to realize the encoding operation in a codec A and the second CPU to realize the decoding operation in a codec B.
Then, the executable code 506 is loaded into the internal memory 101.
If the OS (Operating System) of the information system has dynamic libraries and a link function or supports virtual addresses by hardware, the OS generally can change the address of an executable code during loading of a program. However, in the case where the chip 1 is incorporated in a system provided with an OS having no function like the above-mentioned one or in a system having no OS, the address of an executable code is fixed when the executable code is generated, so that a loading location for the code cannot be dynamically switched.
Accordingly, in order to enable the CPUs to operate by means of a plurality of codecs, it is necessary to hold codes corresponding to all assumable patterns in the internal memory 101 and the like. At this time, if there are a multiplicity of codecs desired to be used and all of the codes are not accommodated in the internal memory 101, the executable codes are held in the external memory 110, the server 120 or the like so that the kind of codec or the operation thereof can be switched by downloading being executed as the occasion demands.
However, as shown in FIG. 6, the code for the first CPU and the code for the second CPU are integrated in the conventional executable code 506, so that if only the operation of either one of the first CPU 103 and the second CPU 104 is to be switched, the whole of the executable code 506 needs to be reloaded into the internal memory 101.
The switching of the operation in the conventional information processing system will be described below with reference to FIGS. 7 and 8. FIG. 7 shows the case where the first to fourth instruction codes 212 to 215 are previously stored in the external memory 110 and the first instruction code 212 is first loaded into the internal memory 101. The second instruction code 213 contains a code which causes the first CPU 103 to perform the encoding operation by means of on a codec A and causes the second CPU 104 to perform the decoding operation by means of a codec D. The third instruction code 214 contains a code which causes the first CPU 103 to perform the encoding operation by means of on a codec C and causes the second CPU 104 to perform the decoding operation by means of a codec B. The fourth instruction code 215 contains a code, which causes the first CPU 103 to perform the encoding operation by means of on the codec C and causes the second CPU 104 to perform the decoding operation by means of the codec D.
The operations of the first and second CPUs 103 and 104 shown in FIG. 7 will be described with reference to FIG. 8. First, in Step S1, the host CPU 111 resets the first CPU 103, and in Step S2, the host CPU 111 writes a bootstrap to the boot memory 105. Then, in Step S3, the host CPU 111 cancels the reset state of the first CPU 103. Then, in Step S4, the first CPU 103 executes the bootstrap written in the boot memory 105, and in Step S5, transfers via DMA, for example, the first instruction code 212 from the external memory 110 to the internal memory 101 by using the DMA controller 102.
In Step S6, after the first CPU 103 confirms the completion of the transfer, the first CPU 103 resets the second CPU 104, and then activates the second CPU 104 by canceling the reset state of the second CPU 104. In Step S7, the first CPU 103 executes the instruction code for the first CPU 103 stored in the internal memory 101.
In this manner, in Step S8, the first CPU 103 operates as the encoder of the codec A, and in Step S9, the second CPU 104 operates as the decoder of the codec B by executing the instruction code for the second CPU 104 stored in the internal memory 101.
At this time, since the instruction code for the first CPU and the instruction code for the second CPU are integrated as one instruction code as mentioned above, if, for example, the first CPU 103 is to be operated as the encoder of the codec C, the whole of the first instruction code 212 loaded in the internal memory 101 needs to be replaced with the third instruction code 214 even if the function of the second CPU 104 does not need to be changed.
Accordingly, the above-mentioned conventional information processing system has the following problems. First, since instructions for the first CPU 103 and instructions for the second CPU 104 are integrally compiled, the combination of instructions which form an executable code is fixed. For this reason, in order to enable a plurality of CPUs to operate by means of a plurality codecs, it is necessary to hold compiled codes corresponding to individual operating states in the external memory 110 (or the server 120 on the network) in advance.
In addition, since one executable code is formed by instructions for the first CPU 103 and instructions for the second CPU 104 as mentioned above, the size of an executable code becomes large. Accordingly, the size of a code to be replaced in the internal memory 101 becomes large, so that code replacement time becomes long.
Furthermore, since one executable code is formed by instructions for the first CPU 103 and instructions for the second CPU 104 as mentioned above, even when, for example, the operation of only the first CPU 103 is to be changed as mentioned above, the operation of the second CPU 104 must also be interrupted. In other words, for example, during the transcoding operation of encoding the result decoded by the second CPU 104 under the codec B, by means of the first CPU 103 under the codec A, only the operation of the first CPU 103 cannot be changed, and the decoder of the second CPU 104 must also be interrupted.
The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide an information processing method for an information processing system having a plurality of CPUs, a program which realizes the information processing method, and a recording medium on which the program is recorded, which method is capable of reducing the necessary storage capacity of the system and enhancing the processing speed thereof, which also is capable of easily changing the function of each of the CPUs without affecting the operation of the other CPUs.